1. Field of the Invention
The present invention generally relates to an information processing device and, more particularly, to a multiprocessor incorporated in a server.
Recently, as the Internet has rapidly become prevalent, the electronic commerce is undergoing a rapid expansion. In the electronic commerce, one has to exchange information with many and unspecified people or businesses, and has to process such information, necessitating a server capable of processing information at high speed. Such a server is required to be highly reliable, and further, to be as small as possible.
Such a server comprises a multiprocessor. Therefore, such a multiprocessor is required to be capable of processing information at high speed, to be highly reliable, and further, to be as small as possible.
One type of such a multiprocessor is an SMP (Symmetric Multiprocessor) wherein all of its CPUs share all of its memories and each of the CPUs accesses each of the memories at the same speed.
The SMP is further classified into a bus type and a crossbar-interconnect type. The bus type is a system wherein all of its CPUs share a single bus. The crossbar-interconnect type is a system wherein all of its CPUs are crossbar-connected to all of its memories, enabling a plurality of the CPUs to simultaneously access different memories. Thus, the crossbar-interconnect type has a better access property than the bus type.
2. Description of the Related Art
FIG. 1 is an illustration of a conventional multiprocessor 10 of the crossbar-interconnect type.
In general, a multiprocessor basically comprises: a backboard; a plurality of crossbar-boards connected to a backside thereof by connectors; and a plurality of motherboards plugged in and connected to a front of the backboard by the connectors. Since a backboard is limited in size due to reasons deriving from a manufacturing process thereof, the maximum number of motherboards connected to the backboard is eight, for example.
The above-mentioned multiprocessor 10 is capable of processing numerous information, and thus requires 16 motherboards, for example. Therefore, the multiprocessor 10 comprises two units 11 and 21 each having a backboard proper in size, the two units 11 and 21 being connected to each other by a multitude of cables 30.
The unit 11 comprises: a backboard 12; a plurality of crossbar-boards 13 connected to a backside thereof by connectors; and eight motherboards 14 plugged in and connected to a front of the backboard 12 by the connectors. The unit 21, in the same manner as the unit 11, comprises: a backboard 22; a plurality of crossbar-boards 23 connected to a backside thereof by connectors; and eight motherboards 24 plugged in and connected to a front of the backboard 22 by the connectors. Each of the motherboards 14 and 24 comprises: a board; and a CPU 15 and a memory module 16 each mounted thereon. Each of the plurality of crossbar-boards 13 and 23 comprises a board and a switching circuit 17 mounted thereon.
The plurality of crossbar-boards 13 of the unit 11 and the plurality of crossbar-boards 23 of the unit 21 are connected by the multitude of cables 30.
The CPUs 15 of the motherboards 14 of the unit 11 are connected to one another by wiring patterns on the crossbar-boards 13. Therefore, a transmission distance of signals between any two of the motherboards 14 is short. However, the CPUs 15 of the motherboards 14 of the unit 11 are connected to the CPUs 15 of the motherboards 24 of the unit 21 by the wiring patterns on the crossbar-boards 13, the cables 30 and wiring patterns on the crossbar-boards 23. Therefore, a transmission distance of signals between any one of the motherboards 14 and any one of the motherboards 24 is long, increasing the likelihood of causing distortion of transmitting signals. The distortion of transmitting signals occurs as an error when raising a transfer rate of signals. Therefore, the transfer rate of signals could not be raised, rather has to be kept low to avoid causing the distortion of transmitting signals. In this way, the multiprocessor 10 has a hindering problem in processing information at high speed.
Additionally, as described above, the multiprocessor 10 comprises the two units 11 and 21 connected to each other by the multitude of cables 30. Thus, manufacturing the multiprocessor 10 requires steps of connecting the multitude of cables 30 one by one. These steps of connecting are not only cumbersome but also prone to error. Further, when even a single cable of the multitude of cables 30 causes a poor connection, the multiprocessor 10 cannot operate normally. These respects arouse another problem in reliability.
Besides, as described above, the multiprocessor 10 comprises the two units 11 and 21 connected to each other by the cables 30, the cables increasing the size of the multiprocessor 10. This is a problem of inevitably increasing the size of a server comprising the multiprocessor 10.